Field of the Invention
The present invention relates to an apparatus for testing a package-on-package device, particularly to an apparatus for testing electrical characteristics or functions of a package-on-package semiconductor device.
Description of the Related Art
FIG. 4 shows a schematic sectional view of a general package-on-package semiconductor device. The so-called package-on-package technology means that two or more elements are packaged in a way of vertical stacking or back carrying. As shown in FIG. 4, generally, the package comprises a lower chip 91 and an upper chip 92, wherein the lower chip 91 is typically an integrated digital or mixed signal logic chip, for example, a baseband processor, or a multimedia processor, and the upper chip 92 is typically an integrated memory chip, for example, DRAM or Flash. Accordingly, the advantages of the stacked package reside in compacting the package so as to reduce the whole volume, simplifying the circuitry of the mother board, as compared with the conventional side-by-side package, and improving the frequency performance by the direct connection of a memory chip with a logic circuit.
FIG. 5 shows a sectional view of a conventional apparatus for testing a package-on-package device. As shown in FIG. 5, the conventional testing apparatus includes a jig head 93 holding the upper chip 92 and a test base 94 carrying the lower chip 91 thereon. During a test process, the jig head 93 is lowered to be in contact with the test base 94, and a plurality of probes 95 disposed on the jig head 93 are in electrical contact with the lower chip 91 so that the upper chip 92 and the lower chip 91 are electrically connected with each other.
However, as the capability of the lower chip 91 to be tested becomes more powerful, the entire test process tends to be complex. The load on either the upper chip 92 or the lower chip 91 becomes larger. As a result, high temperature and great heat occur. On the other hand, materials used for the conventional testing apparatus are mostly engineering plastics, such as PEEK (polyetheretherketone), which is heat resistant but has poor thermal conductivity, and hence it is difficult to dissipate the heat generated during the test process. Since the conventional testing apparatus is not provided with heat dissipation means, accumulation of the heat generated by either the upper chip 92 or the lower chip 91 for a long time may disadvantageously affect the performance or the service life of the chip and even damage the chip.